1. Technical Field
The present invention relates in general to integrated-circuit technology and more particularly to the design of very large-scale integrated circuits. In particular, the present invention relates to the layout of logic cells in a space-efficient and wireable fashion and which can readily be integrated into design automation systems.
2. Description of the Related Art
Distributed multiple clock systems are often necessary for implementing high-performance circuit designs. Modern digital circuitry and computer systems often require the use of such clock-distribution systems. A distributed multiple clock system typically includes multiple clock lines which are distributed physically within a circuit in various locations, lengths, and directions. Such systems are usually controlled by continuous, periodic clock pulses, which allow activity within the system to occur at a fixed time relative to one or more clock pulses.
A problem inherent to these systems is clock skew. Clock skew can occur, for example, in latching circuits where two or more clock signals have travelled through different delay paths to arrive at the same latch. A delay in the amount of time for each signal to arrive at the same latch can result from the physical differences in delay paths (e.g., one path might have a longer length than another), or the differences in the timing of the clocks which provide clock signals to the particular circuit. Such delays, whether due to physical differences in clock paths or clock-timing variations can cause latch transmission gates within the circuit to couple. Clock skew can be described as the time between the latest-arriving clock at any latch point minus the earliest-arriving time of all of the clocks at all of the latch points. Clock-skew conditions can lead to incorrect storage-capacitance values and, ultimately, to poor circuit designs. Another reason to reduce clock skew is that, the smaller the skew, the more time is available for logic calculations.
Clock skew can be reduced by making this time difference as small as possible by, in effect, forcing the delay between the clocks to be constant. However, such a reduction in clock skew is difficult to achieve, particularly if a simultaneous design goal is to achieve an efficient wiring scheme. Reducing clock skew directly contributes to the design of high-performing circuits. Unfortunately, maintaining low clock skew without adversely affecting wireability and overly complicating design automation is difficult. Thus, designing a high-performance circuit having a reliable clock scheme in a space-efficient and wireable fashion and in which clock skew is reduced poses a difficult task to the circuit designer.
Thus, a need exists for a multi-phase clock distribution method and system in which clock skew is effectively reduced, contributing to higher-performance designs. A multi-phase clock distribution method and system would allow for the design of a circuit in which phase differences in clock signals and physical differences in clock paths do not result in clock skew or, at the very least, in negligible clock skew. In addition, a need exists for a clocking scheme in which low clock skew is achieved while resulting in a relatively small impact to wiring overhead. Finally, a need exists for a clocking strategy that can be easily incorporated into design automation systems.